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970 caution: these devices are sensitive to electrostatic discharge; follow proper ic handling procedures. http://www.intersil.com or 407-727-9207 | copyright ? intersil corporation 1999 hs-82c55arh radiation hardened cmos programmable peripheral interface pinout 40 lead ceramic dual-in-line metal seal package (sbdip) mil-std-1835 cdip2-t40 top view pin description pin description d7 - d0 data bus (bi-directional reset reset input cs chip select rd read input wr write input a0 - a1 port address pa7 - pa0 port a (bit) pb& - pb0 port b (bit) pc7 - pc0 port c (bit) vdd +5 volts gnd 0 volts 13 1 2 3 4 5 6 7 8 9 10 11 12 14 15 16 17 18 19 20 pa3 pa2 pa1 pa0 rd cs gnd a1 a0 pc7 pc6 pc5 pc4 pc0 pc1 pc2 pc3 pb0 pb1 pb2 28 40 39 38 37 36 35 34 33 32 31 30 29 27 26 25 24 23 22 21 pa4 pa5 pa6 pa7 wr reset d0 d1 d2 d3 d4 d5 d6 d7 vdd pb7 pb6 pb5 pb4 pb3 features ? radiation hardened - total dose >10 5 rad (si) - transient upset <10 8 rad (si)/s - latch up free epi-cmos ? low power consumption - iddsb = 20 m a ? pin compatible with nmos 8255a and the intersil 82c55a ? high speed, no wait state operation with 5mhz hs-80c86rh ? 24 programmable i/o pins ? bus-hold circuitry on all i/o ports eliminates pull-up resistors ? direct bit set/reset capability ? enhanced control word read capability ? hardened field, self-aligned, junction isolated cmos process ? single 5v supply ? 2.0ma drive capability on all i/o port outputs ? military temperature range: -55 o c to +125 o c description the intersil hs-82c55arh is a high performance, radiation hardened cmos version of the industry standard 8255a and is manufactured using a hardened ?eld, self-aligned silicongate cmos process. it is a general purpose programmable i/o device which may be used with many different microprocessors. there are 24 i/o pins which are organized into two 8-bit and two 4-bit ports. each port may be programmed to function as either an input or an output. additionally, one of the 8-bit ports may be programmed for bi-directional operation,and the two 4-bit ports can be programmed to provide handshaking capabilities. the high performance, radiation hardness, and industry standard con?guration of the hs-82c55arh make it compatible with the hs-80c86rh radiation hardened microprocessor. static cmos circuit design insures low operating power. bus hold circuitry eliminates the need for pull-up resistors. the intersil hardened ?eld cmos process results in performance equal to or greater than existing radiation resistant products at a fraction of the power. ordering information part number temperature package HS1-82C55ARH-q -55 o c to +125 o c 40 lead sbdip HS1-82C55ARH-8 -55 o c to +125 o c 40 lead sbdip HS1-82C55ARH/sample +25 o c 40 lead sbdip september 1995 spec number 518060 file number 3191.1 db na
971 hs-82c55arh pin description symbol pin numbers type description pa0-7 1-4, 37-40 i/o port a: general purpose i/o port. data direction and mode is determined by the contents of the control word. pb0-7 18-25 i/o port b: general purpose i/o port. see port a. pc0-3 14-17 i/o port c (lower): combination i/o port and control port associated with port b. see port a. pc4-7 10-13 i/o port c (upper): combination i/o port and control port associated with port a. see port a. d0-7 27-34 i/o bidirectional data bus: three-state data bus enabled as an input when cs and wr are low and as an output when cs and rd are low. vdd 26 i vdd: the +5v power supply pin. a 0.1 m f capacitor between pins 26 and 7 is recommend- ed for decoupling. gnd 7 i ground . cs 6 i chip select: a low on this input pin enables the communication between the hs-82c55arh and the cpu. rd 5 i read: a low on this input pin enables the hs-82c55arh to send the data or status information to the cpu on the data bus. in essence, it allows the cpu to read from the hs-82c55arh. wr 36 i w rite: a low on this input pin enables the cpu to write data or control words into the hs-82c55arh. a0 and a1 8, 9 i port select 0 and port select 1: these input signals, in conjunction with the rd and wr inputs, control the selection of one of the three ports or the control word registers. they are normally connected to the least signi?cant bits of the address bus (a0 and a1). reset 35 i reset: a high on this input clears the control register and all ports (a, b, c) are set to the input mode. bus hold devices internal to the hs-82c55arh will hold the i/o port inputs to a logic 1 state with a maximum hold current of 400 m a. functional diagram group a control power supplies data bus buffer group b control read/write control logic rd wr a1 a0 reset cs d7 - d0 bidirectional data bus +5v gnd 8-bit internal data bus group b port b (8) group b port c lower (4) group a port c upper (4) group a port a (8) i/o pa7 - pa0 i/o pc7 - pc4 i/o pc3 - pc0 i/o pb7 - pb0 spec number 518060
972 speci?cations hs-82c55arh absolute maximum ratings reliability information supply voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +7.0v input, output or i/o voltage . . . . . . . . . . . . .vss-0.3v to vdd+0.3v storage temperature range . . . . . . . . . . . . . . . . . -65 o c to +150 o c junction temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +175 o c lead temperature (soldering 10s) . . . . . . . . . . . . . . . . . . . . +300 o c esd classi?cation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . class 1 thermal resistance q ja q jc sbdip package. . . . . . . . . . . . . . . . . . . . 40 o c/w 6 o c/w maximum package power dissipation at +125 o c ambient sbdip package. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.25w if device power exceeds package dissipation capability, provide heat sinking or derate linearly at the following rate: sbdip package. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25.0mw/c caution: stresses above those listed in absolute maximum ratings may cause permanent damage to the device. this is a stress o nly rating and operation of the device at these or any other conditions above those indicated in the operational sections of this speci?cation is not im plied. operating conditions operating voltage range . . . . . . . . . . . . . . . . . . . . . +4.5v to +5.5v operating temperature range . . . . . . . . . . . . . . . . -55 o c to +125 o c input low voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .0v to +0.8v input high voltage. . . . . . . . . . . . . . . . . . . . . . . . vdd -1.5v to vdd table 1. dc electrical performance characteristics parameter symbol conditions group a subgroup temperature limits units min max ttl output high voltage voh1 vdd = 4.5v, io = -2.5ma, vin = 0v, 4.5v 1, 2, 3 -55 o c, +25 o c, +125 o c 3.0 - v cmos output high volt- age voh2 vdd = 4.5v, io = -100 m a, vin = 0v, 4.5v 1, 2, 3 -55 o c, +25 o c, +125 o c vdd- 0.4 -v output low voltage vol vdd = 4.5v, io = 2.5ma, vin = 0v, 4.5v 1, 2, 3 -55 o c, +25 o c, +125 o c - 0.4 v input leakage current iil or iih vdd = 5.5v, vin = 0v, 5.5v 1, 2, 3 -55 o c, +25 o c, +125 o c -1.0 1.0 m a output leakage current iozl or iozh vdd = 5.5v, vin = 0v, 5.5v 1, 2, 3 -55 o c, +25 o c, +125 o c -10 10 m a input current bus hold high ibhh vdd = 4.5v or 5.5v, vin = 3.0v (see note 1) ports a, b, c 1, 2, 3 -55 o c, +25 o c, +125 o c -800 -60 m a input current bus hold low ibhl vdd = 4.5v or 5.5v, vin = 1.0v (see note 2) port a 1, 2, 3 -55 o c, +25 o c, +125 o c 60 800 m a standby power supply current iddsb vdd = 5.5v, io = 0ma, vin =gnd or vdd 1, 2, 3 -55 o c, +25 o c, +125 o c -20 m a darlington drive voltage vdar vdd = 4.5v, io = -2.0ma, vin = gnd or vdd 1, 2, 3 -55 o c, +25 o c, +125 o c 3.9 - v functional tests ft vdd = 4.5v and 5.5v, vin = gnd or vdd, f = 1mhz 7, 8a, 8b -55 o c, +25 o c, +125 o c -- - noise immunity functional test (note 4) fn vdd = 5.5v, vin = gnd or vdd - 1.5v and vdd = 4.5v, vin = 0.8v or vdd 7, 8a, 8b -55 o c, +25 o c, +125 o c -- - notes: 1. ibhh should be measured after raising vin and then lowering to 3.0v. 2. ibhl should be measured after lowering vin to vss and then raising to 0.8v. 3. no internal current limiting exists on the port outputs. a resistor must be added externally to limit the current. 4. for vih (vdd = 5.5v) and vil (vdd = 4.5v) each of the following groups is tested separately with all other inputs using vih = 2.6v, vil = 0.4v: pa, pb, pc, control pins (pins 5, 6, 8, 9, 35, 36). spec number 518060
973 speci?cations hs-82c55arh table 2. ac electrical performance characteristics t a = -55 o c to +125 o c parameter symbol conditions sub- groups temperature limits units min max read address stable before rd tavrl vdd = 4.5, 5.5v 9, 10, 11 -55 o c, +25 o c, +125 o c0-ns address stable after rd trhax vdd = 4.5, 5.5v 9, 10, 11 -55 o c, +25 o c, +125 o c0-ns rd pulse width trlrh vdd = 4.5, 5.5v 9, 10, 11 -55 o c, +25 o c, +125 o c 250 - ns data valid from rd trldv vdd = 4.5, 5.5v 9, 10, 11 -55 o c, +25 o c, +125 o c - 200 ns data float after rd trhdx vdd = 4.5, 5.5v 9, 10, 11 -55 o c, +25 o c, +125 o c10- ns time between rds and/ or wrs trwhrwl vdd = 4.5, 5.5v 9, 10, 11 -55 o c, +25 o c, +125 o c 300 - ns write address stable before wr tavwl vdd = 4.5, 5.5v 9, 10, 11 -55 o c, +25 o c, +125 o c0-ns address stable after wr twhax vdd = 4.5, 5.5v, ports a and b 9, 10, 11 -55 o c, +25 o c, +125 o c20- ns vdd = 4.5, 5.5v, port c 9, 10, 11 -55 o c, +25 o c, +125 o c 100 - ns wr pulse width twlwh vdd = 4.5, 5.5v 9, 10, 11 -55 o c, +25 o c, +125 o c 100 - ns data valid to wr high tdvwh vdd = 4.5, 5.5v 9, 10, 11 -55 o c, +25 o c, +125 o c 100 - ns data valid after wr high twhdx vdd = 4.5, 5.5v, ports a and b 9, 10, 11 -55 o c, +25 o c, +125 o c30- ns vdd = 4.5, 5.5v, port c 9, 10, 11 -55 o c, +25 o c, +125 o c 100 - other timings wr = 1 to output twhpv vdd = 4.5, 5.5v 9, 10, 11 -55 o c, +25 o c, +125 o c - 350 ns peripheral data before rd tpvrl vdd = 4.5, 5.5v 9, 10, 11 -55 o c, +25 o c, +125 o c0-ns peripheral data after rd trhpx vdd = 4.5, 5.5v 9, 10, 11 -55 o c, +25 o c, +125 o c0-ns ack pulse width tklkh vdd = 4.5, 5.5v 9, 10, 11 -55 o c, +25 o c, +125 o c 200 - ns stb pulse width tslsh vdd = 4.5, 5.5v 9, 10, 11 -55 o c, +25 o c, +125 o c 100 - ns peripheral data before stb high tpvsh vdd = 4.5, 5.5v 9, 10, 11 -55 o c, +25 o c, +125 o c20- ns peripheral data after stb high tshpx vdd = 4.5, 5.5v 9, 10, 11 -55 o c, +25 o c, +125 o c50- ns ack = 0 to output tklpv vdd = 4.5, 5.5v 9, 10, 11 -55 o c, +25 o c, +125 o c - 175 ns ack = 1 to output float tkhpz vdd = 4.5, 5.5v 9, 10, 11 -55 o c, +25 o c, +125 o c10- ns spec number 518060
974 speci?cations hs-82c55arh wr = 1 to obf = 0 twhol vdd = 4.5, 5.5v 9, 10, 11 -55 o c, +25 o c, +125 o c - 150 ns ack = 0 to obf = 1 tkloh vdd = 4.5, 5.5v 9, 10, 11 -55 o c, +25 o c, +125 o c - 150 ns stb = 0 to ibf = 1 tslih vdd = 4.5, 5.5v 9, 10, 11 -55 o c, +25 o c, +125 o c - 150 ns rd = 1 to ibf = 0 trhil vdd = 4.5, 5.5v 9, 10, 11 -55 o c, +25 o c, +125 o c - 150 ns rd = 0 to intr = 1 trlnl vdd = 4.5, 5.5v 9, 10, 11 -55 o c, +25 o c, +125 o c - 200 ns stb = 1 t intr = 1 tshnh vdd = 4.5, 5.5v 9, 10, 11 -55 o c, +25 o c, +125 o c - 150 ns ack = 1 to intr = 1 tkhnh vdd = 4.5, 5.5v 9, 10, 11 -55 o c, +25 o c, +125 o c - 150 ns wr = 0 to intr = 0 twlnl vdd = 4.5, 5.5v 9, 10, 11 -55 o c, +25 o c, +125 o c - 200 ns reset pulse width trshrsl vdd = 4.5, 5.5v (note 2) 9, 10, 11 -55 o c, +25 o c, +125 o c 500 - ns notes: 1. acs tested at worst case vdd, guaranteed over full operating range. 2. period of initial reset pulse after power-on must be at least 50 m s. subsequenct reset pulses may be 500ns minimum. table 3. electrical performance characteristics parameter symbol conditions temperature limits units min max input capacitance cin vdd = open, f = 1mhz, all measurements referenced to device ground t a = +25 o c - 10 pf i/o capacitance ci/o vdd = open, f = 1mhz, all measurements referenced to device ground t a = +25 o c - 20 pf data float after rd trhdx vdd = 4.5v and 5.5v -55 o c < t a < +125 o c - 75 ns ack = 1 to output float tkhpz vdd = 4.5v and 5.5v -55 o c < t a < +125 o c - 250 ns note: the parameters listed in table 3 are controlled via design or process parameters and are not directly tested. these parame ters are characterized upon initial design release and upon design changes which would affect these characteristics talbe 4. post 100k rad electrical performance characteristics see +25 o c limits in table 1 and table 2 for post rad limits (subgroups 1, 7, 9) table 2. ac electrical performance characteristics t a = -55 o c to +125 o c (continued) parameter symbol conditions sub- groups temperature limits units min max spec number 518060
975 speci?cations hs-82c55arh table 5. burn-in delta parameters (+25 o c) parameter symbol delta limits static current iddsb 10 m a input leakage current iil, iih 200na output leakage current iozl, iozh 2 m a low level output voltage vol 80mv ttl output high voltage voh1 600mv cmos output high voltage voh2 150mv table 6. applicable subgroups conformance group mil-std-883 method group a subgroups tested for -q recorded for -q tested for -8 recorded for -8 initial test 100% 5004 1, 7, 9 1 (note 2) 1, 7, 9 interim test 100% 5004 1, 7, 9, d 1, d (note 2) 1, 7, 9 pda 100% 5004 1, 7, d - 1, 7 final test 100% 5004 2, 3, 8a, 8b, 10, 11 - 2, 3, 8a, 8b, 10, 11 group a (note 1) sample 5005 1, 2, 3, 7, 8a, 8b, 9, 10, 11 - 1, 2, 3, 7, 8a, 8b, 9, 10, 11 subgroup b5 sample 5005 1, 2, 3, 7, 8a, 8b, 9, 10, 11, d 1, 2, 3, d (note 2) n/a subgroup b6 sample 5005 1, 7, 9 - n/a group c sample 5005 n/a n/a 1, 2, 3, 7, 8a, 8b, 9, 10, 11 group d sample 5005 1, 7, 9 - 1, 7, 9 group e, subgroup 2 sample 5005 1, 7, 9 - 1, 7, 9 notes: 1. alternate group a testing in accordance with mil-std-883 method 5005 may be exercised. 2. table 5 parameters only spec number 518060
976 hs-82c55arh intersil space level product flow -q wafer lot acceptance (all lots) method 5007 (includes sem) gamma radiation veri?cation (each wafer) method 1019, 2 samples/wafer, 0 rejects 100% die attach 100% nondestructive bond pull, method 2023 sample - wire bond pull monitor, method 2011 sample - die shear monitor, method 2019 or 2027 100% internal visual inspection, method 2010, condition a csi and/or gsi precap (note 6) 100% temperature cycle, method 1010, condition c, 10 cycles 100% constant acceleration, method 2001, condition per method 5004 100% pind, method 2020, condition a 100% external visual 100% serialization 100% initial electrical test (t0) 100% static burn-in 1, condition a or b, 72 hours min, +125 o c min, method 1015 100% interim electrical test 1 (t1) 100% delta calculation (t0-t1) 100% pda 1, method 5004 (note 1) 100% dynamic burn-in, condition d, 240 hours, +125 o c or equivalent, method 1015 100% interim electrical test 2(t2) 100% delta calculation (t0-t2) 100% pda 2, method 5004 (note 1) 100% final electrical test 100% fine/gross leak, method 1014 100% radiographic (x-ray), method 2012 (note 2) 100% external visual, method 2009 sample - group a, method 5005 (note 3) sample - group b, method 5005 (note 4) sample - group d, method 5005 (notes 4 and 5) 100% data package generation (note 7) csi and/or gsi final (note 6) notes: 1. failures from subgroup 1, 7 and deltas are used for calculating pda. the maximum allowable pda = 5% with no more than 3% of t he failures from subgroup 7. 2. radiographic (x-ray) inspection may be performed at any point after serialization as allowed by method 5004. 3. alternate group a testing may be performed as allowed by mil-std-883, method 5005. 4. group b and d inspections are optional and will not be performed unless required by the p.o. when required, the p.o. should i nclude separate line items for group b test, group b samples, group d test and group d samples. 5. group d generic data, as de?ned by mil-i-38535, is optional and will not be supplied unless required by the p.o. when require d, the p.o. should include a separate line item for group d generic data. generic data is not guaranteed to be available and is theref ore not available in all cases. 6. csi and/or gsi inspections are optional and will not be performed unless required by thep.o. when required, the p.o. should i nclude separate line items for csi precap inspection, csi ?nal inspection, gsi precap inspection, and/or gsi ?nal inspection. 7. data package contents: ? cover sheet (intersil name and/or logo, p.o. number, customer part number, lot date code, intersil part number, lot number, qu an- tity). ? wafer lot acceptance report (method 5007). includes reproductions of sem photos with percent of step coverage. ? gamma radiation report. contains cover page, disposition, rad dose, lot number, test package used, speci?cation numbers, test equipment, etc. radiation read and record data on ?le at intersil. ? x-ray report and ?lm. includes penetrometer measurements. ? screening, electrical, and group a attributes (screening attributes begin after package seal). ? lot serial number sheet (good units serial number and lot number). ? variables data (all delta operations). data is identi?ed by serial number. data header includes lot number and date of test. ? group b and d attributes and/or generic data is included when required by the p.o. ? the certi?cate of conformance is a part of the shipping invoice and is not part of the data book. the certi?cate of conformanc e is signed by an authorized quality representative. spec number 518060
977 hs-82c55arh intersil space level product flow -8 gamma radiation veri?cation (each wafer) method 1019, 2 samples/wafer, 0 rejects 100% die attach periodic- wire bond pull monitor, method 2011 periodic- die shear monitor, method 2019 or 2027 100% internal visual inspection, method 2010, condition b csi an/or gsi precap (note 5) 100% temperature cycle, method 1010, condition c, 10 cycles 100% constant acceleration, method 2001, condition per method 5004 100% external visual 100% initial electrical test 100% dynamic burn-in, condition d, 160 hours, +125 o c or equivalent, method 1015 100% interim electrical test 100% pda, method 5004 (note 1) 100% final electrical test 100% fine/gross leak, method 1014 100% external visual, method 2009 sample - group a, method 5005 (note 2) sample - group b, method 5005 (note 3) sample - group c, method 5005 (notes 3 and 4) sample - group d, method 5005 (notes 3 and 4) 100% data package generation (note 6) csi and/or gsi final (note 5) notes: 1. failures from subgroup 1, 7 are used for calculating pda. the maximum allowable pda = 5%. 2. alternate group a testing may be performed as allowed by mil-std-883, method 5005. 3. group b, c and d inspections are optional and will not be performed unless required by the p.o. when required, the p.o. shoul d include separate line items for group b test, group c test, group c samples, group d test and group d samples. 4. group c and/or group d generic data, as de?ned by mil-i-38535, is optional and will not be supplied unless required by the p. o. when required, the p.o. should include a separate line item for group c generic data and/or group d generic data. generic data is no t guar- anteed to be available and is therefore not available in all cases. 5. csi and/or gsi inspections are optional and will not be performed unless required by thep.o. when required, the p.o. should i nclude separate line items for csi precap inspection, csi ?nal inspection, gsi precap inspection, and/or gsi ?nal inspection. 6. data package contents: ? cover sheet (intersil name and/or logo, p.o. number, customer part number, lot date code, intersil part number, lot number, qu an- tity). ? gamma radiation report. contains cover page, disposition, rad dose, lot number, test package used, speci?cation numbers, test equipment, etc. radiation read and record data on ?le at intersil. ? screening, electrical, and group a attributes (screening attributes begin after package seal). ? group b, c and d attributes and/or generic data is included when required by the p.o. ? the certi?cate of conformance is a part of the shipping invoice and is not part of the data book. the certi?cate of conformanc e is signed by an authorized quality representative. spec number 518060 ac test circuit * includes stray and jig capacitance test conditions definition table v1 r1 r2 c1 1.7v 523 w open 150pf test point from output under test v1 r1 r2 c1* ac testing input, output waveforms note: ac testing: all parameters tested as per test circuits. input rise and fall times are driven at 1v/ns. 1.5v 1.5v 0.4v input 2.8v
978 waveforms figure 1. mode 0 (basic input) figure 2. mode 0 (basic output) figure 3. mode 1 (strobed input) figure 4. mode 1 (strobed output) figure 5. mode 2 (bidirectional) note: any sequence where wr occurs before ack and stb occurs before rd is permissible. figure 6. write timing figure 7. read timing rd input cs, a1, a0 d7 - d0 tpvrl trhpx trlrh tavrl trhax trldv trhdz wr d7 - d0 cs, a1, a0 output twlwh tdvwh twhdx tavwl twhpv twhax stb ibf intr rd input from peripheral tslsh tslih tshpx tpvsh trhil trlnl tshnh wr obf intr ack output twlnl twhol tkloh twhpv tklkh tkhnh wr obf intr ack stb ibf peripheral bus rd data from cpu to hs-82c55arh twhol tslih tkloh tklkh data from peri- pheral to data from hs-82c55arh hs-82c55arh to peripheral data from hs-82c55arh to cpu tslsh tklpv tkhpx tpvsh tshpx trhil a0 - a1, cs data bus wr tavwl twhax twlwh twhdx tdvwh a0 - a1, cs rd data bus tavrl trhax high impedance valid high impedance trlrh tavrl trhdx hs-82c55arh spec number 518060
979 hs-82c55arh burn-in circuits programmable peripheral interface static configuration notes: 1. vdd = 6.0v 0. 5% 2. idd <500 m a 3. t a min = +125 o c programmable peripheral interface dynamic configuration notes: 1. vdd = 6.0v 5% for burn-in 2. vdd = 5.0v 5% for life test 3. all resistors are 10k w 5% 4. -0.3v vil 0.8v 5. vdd - 1.0v vih vdd 6. idd < 5ma 7. f0 = 10khz, 50% duty cycle 8. f1 = f0/2; f2 = f1/2; f3 = f2/2; f4 = f3/2 . . . f7 = f6/2 9. t a min = +125 o c 13 1 2 3 4 5 6 7 8 9 10 11 12 14 15 16 17 18 19 20 28 40 39 38 37 36 35 34 33 32 31 30 29 27 26 25 24 23 22 21 vdd 13 1 2 3 4 5 6 7 8 9 10 11 12 14 15 16 17 18 19 20 28 40 39 38 37 36 35 34 33 32 31 30 29 27 26 25 24 23 22 21 f0 f4 f6 f5 f7 f3 vdd f0 f2 f1 f5 f0 f0 f4 spec number 518060
980 hs-82c55arh irradiation circuit cmos programmable peripheral interface note: 1. vdd = 5.5v 13 1 2 3 4 5 6 7 8 9 10 11 12 14 15 16 17 18 19 20 28 40 39 38 37 36 35 34 33 32 31 30 29 27 26 25 24 23 22 21 +5.5v +5.5v spec number 518060
981 hs-82c55arh functional description the hs-82c55arh is a programmable peripheral interface designed to allow microcomputer systems to control and interface with all types of peripheral devices.it has the ability to generate and respond to all asynchronous hand- shaking signals necessary to transfer data to and from peripheral devices, and it can also interrupt the processor when a peripheral needs servicing. these capabilities allow the hs-82c55arh to be used in an unlimited number of applications including external system control, asynchronous data transfer, and systems monitoring. data bus buffer this tri-state bidirectional 8-bit buffer is used to interface the hs-82c55arh to the system data bus (see figure 8). data is transmitted or received by the buffer upon execution of input or output instructions by the cpu. control words and status information are also transferred through the data bus buffer. figure 8. block diagram data bus buffer, read/write, group a and b control logic functions read/write and control logic the function of this block is to manage all of the internal and external transfer of both data and control or status words. it accepts inputs from the cpu address and control busses and in turn, issues commands to both of the control groups. group a and group b controls the functional con?guration of each port is programmed by the systems software. in essence, the cpu writes a control word to the hs-82c55arh. the control word contains infor- mation such as mode, bit set, bit reset, etc., that initial- izes the functional con?guration of the hs-82c55arh. each of the control blocks (group a and group b) accepts commands from the read/write control logic, receives control words from the internal data bus and issues the proper commands to its associated ports. control group - port a and port c upper (c7 - c4) control group - port b and port c lower (c3 - c0). group power supplies data bus buffer group read/ rd wr a1 a0 reset cs d7- bidirectional data bus +5v gnd 8-bit internal data bus group b port b (8) group b port c lower group a port c upper group a port a (8) i/o pa 7- write control logic d0 pa0 i/o pc 7- pc4 i/o pc3- pc0 i/o pb 7- pb0 a control b control (4) (4) ports a, b, c the hs-82c55arh contains three 8-bit ports (a, b and c). all can be con?gured to a wide variety of functional characteristics by the system software but each has its own special features or personality to further enhance the power and ?exibility of the hs-82c55arh. (a) (b) figure 9. i/o port configuration operational description control word the data direction and mode of ports a, b and c are determined by the contents of the control word. see figure 11. the control word can be both written and read as shown in table 1 and 2. during write operations, the function of the control word being written is determined by data bit d7. if d7 is low, the data on d0 - d3 will set or reset one of the bits of port c. see figure 12. during read operations, the port a one 8-bit data output latch/buffer and one 8-bit data input latch. both pull-up and pull-down bus hold devices are present on port a. see figure 9a. port b one 8-bit data input/output latch/buffer and one 8- bit data input buffer. see figure 9b. port c one 8-bit data output latch/buffer and one 8-bit data input buffer (no latch for input). this port can be divided into two 4-bit ports under the mode control. each 4-bit port contains a 4-bit latch and can be used for the control signal outputs and status signal inputs in conjunction with ports a and b. see figure 9b. master reset internal data in internal data out wr signal rd control external port a pin master reset internal data in internal data out wr signal external port b, c p vdd pin spec number 518060
982 hs-82c55arh control word will always be in the format illustrated in figure 11 with bit d7 high to indicate control word mode informa- tion. figure 10. basic mode definitions & bus interface table 1. a1 a0 rd wr cs input operation (read) 00010 port a - data bus 01010 port b - data bus 10010 port c - data bus 11010 control word - data bus table 2. a1 a0 rd wr cs output operation (write) 00100 data bus - port a 01100 data bus - port b 10100 data bus - port c 11100 data bus - control word rd, wr d7 - d0 a0 - a1 bca cs 8 4 8 4 i/o i/o i/o i/o pb7 - pb0 pc3 - pc0 pc7 - pc4 pa7 - pa0 mode 0 data bus control bus address bus bca 8 8 i/o i/o pb7 - pb0 pa7 - pa0 mode 1 control or i/o control or i/o bca 8 8 i/o bidirec- pb7 - pb0 pa7 - pa0 mode 2 i/o control tional figure 11. mode set control word format mode selection there are three basic modes of operation that can be selected by the system software: when the reset input goes high, all ports will be set to the input mode with all 24 port lines held at the logic one level by internal bus hold devices. after reset, the hs- 82c55arh can remain in the input mode with no additional initialization required. this eliminates the need for pullup or pulldown resistors in all cmos designs. during the execution of the system program, any of the other modes may be selected using a single output instruction. this allows a single hs-82c55arh to service a variety of peripheral devices with a simple software maintenance routine. the modes for port a and port b can be separately de?ned while port c is divided into two portions as required by the port a and port b de?nitions. all of the output registers, including the status register, will be reset whenever the mode is changed. modes may be combined so that their functional de?nition can be tailored to almost any i/o struc- ture. for instance: group b can be programmed in mode 0 to monitor simple switch closings or display computational results, group a could be programmed in mode 1 to monitor a keyboard or tape recorder on an interrupt-driven basis. table 3. a1 a0 rd wr cs disable function xxxx1 data bus - 3-state x x 1 1 0 data bus - 3-state mode 0 - basic input/output mode 1 - strobed input/output mode 2 - bidirectional bus d7 d6 d5 d4 d3 d2 d1 d0 control word group b port c (lower) 1 = input 0 = output port b 1 = input 0 = output mode selection 0 = mode 0 1 = mode 1 group a port c (upper) 1 = input 0 = output port a 1 = input 0 = output mode selection 00 = mode 0 01 = mode 1 1x = mode 2 mode set flag 1 = active spec number 518060
983 hs-82c55arh the mode de?nitions and possible mode combinations may seem confusing at ?rst but after a cursory review of the complete device operation a simple, logical i/o approach will surface. the design of the hs-82c55arh has taken into account things such as ef?cient pc board layout, control signal de?nition vs pc layout and complete functional ?exibility to support almost any peripheral device with no external logic. such design represents the maximum use of the available pins. figure 12. bit set/reset control word format single bit/set/reset feature any of the eight bits of port c can be set or reset using a single output instruction. see figure 12. this feature reduces software requirements in control-based applications. d7 d6 d5 d4 d3 d2 d1 d0 control word bit set/reset 1 = set 0 = reset bit select 0 0 0 0 1 1 0 0 2 0 1 0 3 1 1 0 4 0 0 1 5 1 0 1 6 0 1 1 7 1 1 1 b0 b1 b2 bit set/reset flag 0 = active dont care xxx interrupt control functions when the hs-82c55arh is programmed to operate in mode 1 or mode 2, control signals are provided that can be used as interrupt request inputs to the cpu. the interrupt request signals, generated from port c, can be inhibited or enable by setting or resetting the associated inte ?ip-?op, using the bit set/reset function of port c. this function allows the programmer to enable or disable a cpu interrupt by a speci?c i/o device without affecting any other device in the interrupt structure. inte flip-flop de?nition: (bit-set) - inte is set - interrupt enable. (bit-reset) - inte is reset - interrupt disable. note: all mask ?ip-?ops are automatically reset during mode selection and device reset. operating modes mode 0 (basic input/output) this functional con?guration provides simple input and out- put operations for each of the three ports. no handshaking it required, data is simply written to or read from a speci?c port. mode 0 basic functional de?nitions: ? two 8-bit ports and two 4-bit ports ? any port can be input or output ? outputs are latched ? inputs are not latched ? 16 different input/output con?gurations possible figure 13. mode 0 (basic input) figure 14. mode 0 (basic output) trlrh tpvrl trhpx tavrl trhax trldv trhdx rd input cs, a1, a0 d7 - d0 wr d7 - d0 cs, a1, a0 output twlwh tdvwh twhdx tavwl twhax twhpv spec number 518060
984 hs-82c55arh mode 0 port de?nition a b group a no. group b d4 d3 d1 d0 port a port c (upper) port b port c (lower) 0000 output output 0 output output 0001 output output 1 output input 0010 output output 2 input output 0011 output output 3 input input 0100 output input 4 output output 0101 output input 5 output input 0110 output input 6 input output 0111 output input 7 input input 1000 input output 8 output output 1001 input output 9 output input 1010 input output 10 input output 1011 input output 11 input input 1100 input input 12 output output 1101 input input 13 output input 1110 input input 14 input output 1111 input input 15 input input mode 0 con?gurations control word #0 control word #1 control word #2 control word #3 d7 d6 d5 d4 d3 d2 d1 d0 10000000 a c b 8 4 4 8 pa7 - pa0 pc7 - pc4 pc3 - pc0 pb7 - pb0 d7 - d0 d7 d6 d5 d4 d3 d2 d1 d0 10000001 a c b 8 4 4 8 pa7 - pa0 pc7 - pc4 pc3 - pc0 pb7 - pb0 d7 - d0 d7 d6 d5 d4 d3 d2 d1 d0 10000010 a c b 8 4 4 8 pa7 - pa0 pc7 - pc4 pc3 - pc0 pb7 - pb0 d7 - d0 d7 d6 d5 d4 d3 d2 d1 d0 10000011 a c b 8 4 4 8 pa7 - pa0 pc7 - pc4 pc3 - pc0 pb7 - pb0 d7 - d0 spec number 518060
985 hs-82c55arh control word #4 control word #5 control word #6 control word #7 control word #8 control word #9 control word #10 control word #11 mode 0 con?gurations (continued) d7 d6 d5 d4 d3 d2 d1 d0 10001000 a c b 8 4 4 8 pa7 - pa0 pc7 - pc4 pc3 - pc0 pb7 - pb0 d7 - d0 d7 d6 d5 d4 d3 d2 d1 d0 10011001 a c b 8 4 4 8 pa7 - pa0 pc7 - pc4 pc3 - pc0 pb7 - pb0 d7 - d0 d7 d6 d5 d4 d3 d2 d1 d0 10001010 a c b 8 4 4 8 pa7 - pa0 pc7 - pc4 pc3 - pc0 pb7 - pb0 d7 - d0 d7 d6 d5 d4 d3 d2 d1 d0 10001011 a c b 8 4 4 8 pa7 - pa0 pc7 - pc4 pc3 - pc0 pb7 - pb0 d7 - d0 d7 d6 d5 d4 d3 d2 d1 d0 10010000 a c b 8 4 4 8 pa7 - pa0 pc7 - pc4 pc3 - pc0 pb7 - pb0 d7 - d0 d7 d6 d5 d4 d3 d2 d1 d0 10010001 a c b 8 4 4 8 pa7 - pa0 pc7 - pc4 pc3 - pc0 pb7 - pb0 d7 - d0 d7 d6 d5 d4 d3 d2 d1 d0 10010010 a c b 8 4 4 8 pa7 - pa0 pc7 - pc4 pc3 - pc0 pb7 - pb0 d7 - d0 d7 d6 d5 d4 d3 d2 d1 d0 10010011 a c b 8 4 4 8 pa7 - pa0 pc7 - pc4 pc3 - pc0 pb7 - pb0 d7 - d0 spec number 518060
986 hs-82c55arh control word #12 control word #13 control word #14 control word #15 mode 0 con?gurations (continued) d7 d6 d5 d4 d3 d2 d1 d0 10011000 a c b 8 4 4 8 pa7 - pa0 pc7 - pc4 pc3 - pc0 pb7 - pb0 d7 - d0 d7 d6 d5 d4 d3 d2 d1 d0 10011001 a c b 8 4 4 8 pa7 - pa0 pc7 - pc4 pc3 - pc0 pb7 - pb0 d7 - d0 d7 d6 d5 d4 d3 d2 d1 d0 10011010 a c b 8 4 4 8 pa7 - pa0 pc7 - pc4 pc3 - pc0 pb7 - pb0 d7 - d0 d7 d6 d5 d4 d3 d2 d1 d0 10011011 a c b 8 4 4 8 pa7 - pa0 pc7 - pc4 pc3 - pc0 pb7 - pb0 d7 - d0 operating modes mode 1 (strobed input/output) this functional con?guration provides a means for transfer- ring i/o data to or from a speci?ed port in conjunction with strobes or handshaking signals. in mode 1, port a and port b use the lines on port c to generate or accept these hand- shaking signals. mode 1 basic functional de?nitions: ? two groups (group a and group b) ? each group contains one 8-bit port and one 4-bit control/ data port. ? the 8-bit data port can be either input or output. both inputs and outputs are latched. ? the 4-bit port is used for control and status of the 8-bit port. input control signal de?nition stb (strobe input) a low on this input loads data into the input latch. ibf (input buffer full f/f) a high on this output indicates that the data has been loaded into the input latch; in essence, an acknowledgment. ibf is set by stb input being low and is reset by the rising edge of the rd input. intr (interrupt request) a high on this output can be used to interrupt the cpu when an input device is requesting service. intr is set by the rising edge of stb and reset by the falling edge of rd. this procedure allows an input device to request service from the cpu by simply strobing its data into the port. inte a controlled by bit set/reset of pc4. inte b controlled by bit set/reset of pc2. figure 15. mode 1 input inte a pc6, 7 1 = input 0 = output d7 d6 d5 d4 d3 d2 d1 d0 1 control word mode 1 (port b) 11 pa7 - pa0 pc4 pc5 pc3 pc6, 7 rd 8 stb ibf intr i/o 2 inte b pb7 - pb0 pc2 pc1 pc0 rd 8 stb ibf intr b b b a a a d7 d6 d5 d4 d3 d2 d1 d0 10111/0 control word mode 1 (port a) spec number 518060
987 hs-82c55arh figure 16. mode 1 (strobed input) output control signal de?nition obf (output buffer full f/f) the obf output will go low to indicate that the cpu has written data out to the speci?ed port. this does not mean valid data is sent out of the port at this time since obf can go true before data is available. data is guaranteed valid at the rising edge of obf. see note 1. the obf f/f will be set by the rising edge of the wr input and reset by ack input being low. ack (acknowledge input) a low on this input informs the hs-82c55arh that the data from port a or port b is ready to be accepted. in essence, a response from the peripheral device indicating that it is ready to accept data. see note 1. intr (interrupt request) a high on this output can be used to interrupt the cpu when an output device has accepted data transmitted by the cpu. intr is set by the rising edge of ack and reset by the falling edge of wr. figure 17. mode 1 output stb ibf intr rd input from peripheral tslsh tslih tshpx tpvsh trhil trlnl tshnh inte a d7 d6 d5 d4 d3 d2 d1 d0 1 control word mode 1 (port b) 10 pa7 - pa0 pc7 pc6 pc3 pc4, 5 wr 8 obf ack intr i/o 2 a a a inte b pb7 - pb0 pc1 pc2 pc0 wr 8 obf ack intr b b b d7 d6 d5 d4 d3 d2 d1 d0 10101/0 control word pc4, 5 1 = input 0 = output mode 1 (port a) inte a controlled by bit set/reset of pc6. inte b controlled by bit set/reset of pc2. figure 18. mode 1 (strobed output) note: 1. to strobe data into the peripheral device, the user must operate the strobe line in a hand shaking mode. the user needs to send obf to the peripheral device, generate an ack from the periph- eral device and then latch data into the peripheral device on the rising edge of obf. combinations of mode 1: port a and port b can be individu- ally de?ned as input or output in mode 1 to support a wide variety of strobed i/o applications. figure 19. combinations of mode 1 wr obf intr ack output twlnl twhol tkhol twhpv tklkh tkhnh d7 d6 d5 d4 d3 d2 d1 d0 1 control word port a (strobed input) 10 port b (strobed output) 0 1 1 1/0 pc6, 7 1 = input 0 = output pa7 - pa0 pc4 pc5 pc6, 7 wr 8 stb a ibf a intr a pc3 pb7 - pb0 pc1 pc2 pc0 i/o obf b ack b intr b 8 2 rd d7 d6 d5 d4 d3 d2 d1 d0 1 control word port a (strobed output) 11 port b (strobed input) 0 1 0 1/0 pc4, 5 1 = input 0 = output pa7 - pa0 pc7 pc6 pc4, 5 rd 8 obf a ack a intr a pc3 pb7 - pb0 pc2 pc1 pc0 i/o stb b ibf b intr b 8 2 wr spec number 518060
988 hs-82c55arh operating modes mode 2 (strobed bidirectional bus i/o) the functional con?guration provides a means for communi- cating with a peripheral device or structure on a single 8-bit bus for both transmitting and receiving data (bidirectional bus i/o). handshaking signals are provided to maintain proper bus ?ow discipline similar to mode 1. interrupt gen- eration and enable/disable functions are also available. mode 2 basic functional de?nitions: ? used in group a only. ? one 8-bit, bidirectional bus port (port a) and a 5-bit control port (port c). ? both inputs and outputs are latched. ? the 5-bit control port (port c) is used for control and status for the 8-bit, bidirectional bus port (port a). bidirectional bus i/o control signal de?nition intr (interrupt request) a high on this output can be used to interrupt the cpu for both input or output operations. intr will be set either by the rising edge of ack (inte1 = 1) or the rising edge of stb (inte2 = 1). intr will be reset by the falling edge of wr (if previously set by the rising edge or ack), the falling edge of rd (if previously set by the rising edge of stb), or the falling edge of wr when immediately following a low rd pulse or the falling edge of rd when immediately following a low wr pulse (if previously set by the rising edges of both ack and stb). output operations obf (output buffer full) the obf output will go low to indicate that the cpu has written data out to port a. ack (acknowledge) a low on this input enables the tri-state output buffer of port a to send out the data. otherwise, the output buffer will be in the high impedance state. inte 1 (the inte flip-flop associated with obf) controlled by bit set/reset of pc6. input operations stb (strobe input) a low on this input loads data into the input latch. ibf (input buffer full f/f) a high on this output indicates that data has been loaded into the input latch. inte 2 (the inte flip-flop associated with ibf) controlled by bit set/reset of pc4. figure 20. mode control word figure 21. mode 2 (bidirectional) note: any sequence where wr occurs before ack and stb occurs before rd is permissible. figure 22. mode 2 (bidirectional) d7 d6 d5 d4 d3 d2 d1 d0 1 control word 0 1/0 1/0 1/0 pc2 - pc0 1 = input 0 = output port b 1 = input 0 = output group b mode 0 = mode 0 1 = mode 1 inte 2 pc7 pc6 pc3 pc2- pc0 wr 8 stb a ibf a intr a i/o 3 rd pc7 pc6 obf a ack a inte 1 pa7- pa0 wr obf intr ack stb ibf peripheral bus rd data from cpu to hs-82c55arh twhol tslih tkhol tklkh data from peri- pheral to data from hs-82c55arh hs-82c55arh to peripheral data from hs-82c55arh to cpu tslsh tklpv tkhpx tpvsh tshpx trhil spec number 518060
989 hs-82c55arh mode definition summary mode 0 mode 1 mode 2 in out in out group a only pa0 ap1 pa2 pa3 pa4 pa5 pa6 pa7 in in in in in in in in out out out out out out out out in in in in in in in in out out out out out out out out pb0 pb1 pb2 pb3 pb4 pb5 pb6 pb7 in in in in in in in in out out out out out out out out in in in in in in in in out out out out out out out out - - - - - - - - pc0 pc1 pc2 pc3 pc4 pc5 pc6 pc7 in in in in in in in in out out out out out out out out intr b ibf b stb b intr a stb a ibf a i/o i/o intr b obf b ack b intr a i/o i/o ack a obf a i/o i/o i/o intr a stb a ibf a ack a obf a mode 0 or mode 1 only special mode combination considerations there are several combinations of modes possible. for any combination, some or all of port c lines are used for control or status. the remaining bits are either inputs or outputs as de?ned by a set mode command. during a read of port c, the state of all the port c lines, except the ack and stb lines, will be placed on the data bus. in place of the ack and stb line states, ?ag status will appear on the data bus in the pc2, pc4, and pc6 bit positions as illustrated by figure 25. through a write port c command, only the port c pins pro- grammed as outputs in a mode 0 group can be written. no other pins can be affected by a write port c command, nor can the interrupt enable ?ags be accessed. to write to any port c output programmed as an output in a mode 1 group or to change an interrupt enable ?ag, the set/reset port c bit command must be used. with a set/reset port c bit command, any port c line programmed as an output (including ibf and obf) can be written, or an interrupt enable ?ag can be either set or reset. port c lines programmed as inputs, including ack and stb lines, associated with port c fare not affected by a set/ reset port c bit command. writing to the corresponding port c bit positions of the ack and stb lines with the set/ reset port c bit command will affect the group a and group b interrupt enable ?ags, as illustrated in figure 25. figure 23. mode 1 status word format figure 24. mode 2 status word format input configuration d7 d6 d5 d4 d3 d2 d1 d0 i/o i/o ibfa intea intra inteb ibfb intrb group a group b output configuration d7 d6 d5 d4 d3 d2 d1 d0 obfa intea i/o i/o intra inteb obfb intrb group a group b d7 d6 d5 d4 d3 d2 d1 d0 obfa inte1 ibfa inte2 intra x x x group a group b note: (de?ned by mode 0 or mode 1 selection) spec number 518060
990 hs-82c55arh current drive capability any output on port a, b or c can sink or source 2.5ma. this feature allows the 82c55a to directly drive darlington type drivers and high-voltage displays that require such sink or source current. reading port c status (figures 23 and 24) in mode 0, port c transfers data to or from the peripheral device. when the 82c55a is programmed to function in modes 1 or 2, port c generates or accepts hand shaking signals with the peripheral device. reading the contents of port c allows the programmer to test or verify the status of each peripheral device and change the program ?ow accordingly. there is no special instruction to read the status information from port c. a normal read operation of port c is executed to perform this function. figure 25. interrupt enable flags in modes 1 and 2 interrupt enable flag* position alternate port c pin signal (mode) inte b pc2 ackb (output mode 1) or stbb (input mode 1) inte a2 pc4 stba (input mode 1 or mode 2) inte a1 pc6 acka (output mode 1 or mode 2) spec number 518060
991 hs-82c55arh metallization topology die dimensions: 3420 m m x 4350 m m x 485 m m 25 m m metallization: type: al/si thickness: 11k ? 2k ? glassivation: type: sio2 thickness: 8k ? 1k ? worst case current density: 7.7 x 10 4 a/cm 2 metallization mask layout hs-82c55arh (5) rd (4) pa0 (3) pa1 (2) pa2 (1) pa3 (40) pa4 (39) pa5 (38) pa6 (37) pa7 (36) wr reset (35) d0 (34) d1 (33) d2 (32) d3 (31) d4 (30) d5 (29) d6 (28) d7 (27) vdd (26) (6) cs (7) vss (8) a1 (9) a0 (10) pc7 (11) pc6 (12) pc5 (13) pc4 (14) pc0 (15) pc1 pc2 (16) pc3 (17) pb0 (18) pb1 (19) pb2 (20) pb3 (21) pb4 (22) pb5 (23) pb6 (24) pb7 (25) spec number 518060
992 all intersil semiconductor products are manufactured, assembled and tested under iso9000 quality systems certi?cation. intersil products are sold by description only. intersil corporation reserves the right to make changes in circuit design and/o r speci?cations at any time without notice. accordingly, the reader is cautioned to verify that data sheets are current before placing orders. information furnishe d by intersil is believed to be accurate and reliable. however, no responsibility is assumed by intersil or its subsidiaries for its use; nor for any infringements of p atents or other rights of third parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of intersil or its subsidiaries. for information regarding intersil corporation and its products, see web site http://www.intersil.com sales of?ce headquarters north america intersil corporation p. o. box 883, mail stop 53-204 melbourne, fl 32902 tel: (407) 724-7000 fax: (407) 724-7240 europe intersil sa mercure center 100, rue de la fusee 1130 brussels, belgium tel: (32) 2.724.2111 fax: (32) 2.724.22.05 asia intersil (taiwan) ltd. taiwan limited 7f-6, no. 101 fu hsing north road taipei, taiwan republic of china tel: (886) 2 2716 9310 fax: (886) 2 2715 3029 hs-82c55arh spec number

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